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INTEGRATED CIRCUITS
SC68C562 CMOS dual universal serial communications controller (CDUSCC)
Product specification Supersedes data of 1994 Apr 27 IC19 Data Handbook 1998 Sep 04
Philips Semiconductors
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
DESCRIPTION
The Philips Semiconductors SC68C562 Dual Universal Serial Communications Controller (CDUSCC) is a single-chip CMOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SC68C562 interfaces to the 68000 MPUs via asynchronous bus control signals and is capable of program-polled, interrupt driven, block-move or DMA data transfers. The SC68C562 is hardware (pin) and software (Register) compatible with SCN68562 (NMOS version). It will automatically configure to NMOS DUSCC register map on power-up or reset. The operating mode and data format of each channel can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multifunction counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock. This makes the CDUSCC well suited for dual speed channel applications. Data rates up to 10Mb/s are supported. Each transmitter and each receiver is serviced by a 16 byte FIFO. The receiver FIFO also stores 9 status bits for each character received; the transmit FIFO is able to store transmitter commands with each byte. This permits reading and writing of up to 16 bytes at a time, thus minimizing the potential for transmitter underrun, receiver overrun and reducing interrupt or DMA overhead. In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full. Two modem control inputs (DCD and CTS) and three modem control outputs (RTS and two general purpose) are provided. Because the modem control inputs are general purpose in nature, they can be optionally programmed for other functions. This document contains the electrical specifications for the SC68C562. Refer to the CMOS Dual Universal Serial Communications Controller (CDUSCC) User Manual for a complete operational description of this product.
* 0 to 10MHz data rate * Programmable bit rate for each receiver and transmitter selectable
from: - 19 fixed rates: 50 to 64k baud - One user-defined rate derived from programmable counter/timer - External 1X or 16X clock - Digital phase-locked loop
* Parity and FCS (frame check sequence LRC or CRC) generation
and checking
* Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
* Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
* Programmable data transfer mode: polled, interrupt, DMA, wait * DMA interface
- Compatible with the Philips Semiconductors SCB68430 Direct Memory Access Interface (DMAI) and other DMA controllers - Single- or dual-address dual transfers - Half- or full-duplex operation - Automatic frame termination on counter/timer terminal count or DMA DONE
* Transmit path clear status * Interrupt capabilities
- Daisy chain option - Vector output (fixed or modified by status) - Programmable internal priorities - Interrupt at any FIFO fill level - Maskable interrupt conditions
* FIFO'd status bits * Watchdog timer * Multi-function programmable 16-bit counter/timer
- Bit rate generator - Event counter - Count received or transmitted characters - Delay generator - Automatic bit length measurement
FEATURES
* Full hardware and software upward compatibility with previous
NMOS device
* Modem controls
- RTS, CTS, DCD, and up to four general I/O pins per channel - CTS and DCD programmable auto-enables for Tx and Rx - Programmable interrupt on change of CTS or DCD
General Features
transmitter
* Dual full-duplex synchronous/ asynchronous receiver and * Low power CMOS process * Multiprotocol operation
- BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level, etc. - COP: BISYNC, DDCMP - ASYNC: 5-8 bits plus optional parity
* On-chip oscillator for crystal * TTL compatible * Single +5V power supply
Asynchronous Mode Features
* Sixteen character receiver and transmitter FIFOs
1998 Sep 04 2
* Character length: 5 to 8 bits * Odd or even parity, no parity, or force parity * Up to two stop bits programmable in 1/16-bit increments
853-1682 19973
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
* 1X or 16X Rx and Tx clock factors * Parity, overrun, and framing error detection * False start bit detection * Start bit search 1/2-bit time after framing error detection * Break generation with handshake for counting break characters * Detection of start and end of received break * Character compare with optional interrupt on match * Transmits up to 10Mb/s at 1X and receive up to 1Mb/s at 16X
data rates
SC68C562
* Auto transparent mode switching * Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
* Control character sequence detection for both transparent and
normal text
Bit-Oriented Protocol Features
Character-Oriented Protocol Features
* Character length: 5 to 8 bits * Odd or even parity, no parity, or force parity * LRC or CRC generation and checking * Optional opening PAD transmission * One or two SYN characters * External sync capability * SYN detection and optional stripping * SYN or MARK line fill on underrun * Idle in MARK or SYNs * Parity, FCS, overrun, and underrun error detection
BISYNC Features
* Character length: 5 to 8 bits * Detection and transmission of residual character: 0-7 bits * Automatic switch to programmed character length for I field * Zero insertion and deletion * Optional opening PAD transmission * Detection and generation of FLAG, ABORT, and IDLE bit patterns * Detection and generation of shared (single) FLAG between
frames
* Detection of overlapping (shared zero) FLAGs * ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun * Idle in MARK or FLAGs * Secondary address recognition including group and global
address
* EBCDIC or ASCII header, text and control messages * SYN, DLE stripping * EOM (end of message) detection and transmission
ORDERING INFORMATION
DESCRIPTION
* Single- or dual-octet secondary address * Extended address and control fields * Short frame rejection for receiver * Detection and notification of received end of message * CRC generation and checking * SDLC loop mode capability
VCC = +5V 10%, TA = 0 to +70C Serial Data Rate = 10Mbps Maximum SC68C562C1N SC68C562C1A
VCC = +5V 10%, TA = -40 to +85C Serial Data Rate = 8Mbps Maximum Not available SC68C562A8A
DWG #
48-Pin Plastic Dual In-Line Package (DIP) 52-Pin Plastic Leaded Chip Carrier (PLCC) Package
SOT240-1 SOT238-3
ABSOLUTE MAXIMUM RATINGS1
SYMBOL TA TSTG VCC VS PARAMETER Operating ambient temperature2 Storage temperature Voltage from VCC to GND3 Voltage from any pin to ground3 RATING COMMERCIAL 0 to +70 -65 to +150 -0.5 to +7.0 -0.5 to VCC +0.5 INDUSTRIAL -40 to +85 -65 to +150 -0.5 to +7.0 -0.5 to VCC +0.5 UNIT C C V V
1998 Sep 04
3
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
PIN CONFIGURATIONS
N PACKAGE
IACKN A3 A2 A1 RTxDAKBN/ GPI1BN IRQN RESETN RTSBN/ SYNOUTBN TRxCB 1 2 3 4 5 6 7 8 9 48 VDD 47 46 45 44 43 42 41 40 39 DIP 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A4 A5 A6 RTxDAKAN/ GPI1AN X1/CLK X2/IDCN RTSAN/ SYNOUTAN TRxCA RTxCA DCDAN/ SYNIAN Rxda TxDA TxDAKAN/ GPI2AN RTxDRQAN/ GPO1AN TxDRQAN/ GPO2AN/RTSAN CTSAN/LCAN D0 D1 D2 D3 DONEN R/WN CSN 20 21 Pin Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 33 TOP VIEW Pin Function 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 CSN R/WN DONEN D3 D2 D1 D0 NC CTSAN/LCAN TxDRQAN/ GPO2AN/RTSAN RTxDRQAN/ GPO1AN TxDAKAN/ GPI2AN TxDA RxDA NC DCDAN/ SYNIAN RTxCA TRxCA RTSAN/ SYNOUTAN X2/IDCN X1/CLK RTxDAKAN/ GPI1AN A6 A5 A4 VDD 34 PLCC INDEX CORNER 8
A PACKAGE
7 1 47 46
RTxCB 10 DCDBN/ 11 SYNIBN RxDB 12 TxDB 13 TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN 14 15 16 17
D7 18 D6 19 D5 20 D4 21 DTACKN 22 DTCN 23 GND 24
IACKN A3 A2 A1 RTxDAKBN/ GPI1BN IRQN NC RESETN RTSBN/ SYNOUTBN TRxCB RTxCB DCDBN/ SYNIBN NC RxDB TxDB TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN D7 D6 D5 D4 DTACKN DTCN GND
SD00222
1998 Sep 04
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Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
BLOCK DIAGRAM
CHANNEL MODE AND TIMING A/B DPLL CLK MUX A/B INTERFACE/ OPERATION CONTROL ADDRESS DECODE R/W DECODE MPU INTERFACE DMA CONTROL CCRA/B RTxDRQAN/GPO1AN RTxDRQBN/GPO1BN TxDRQAN/GPO2AN TxDRQBN/GPO2BN RTxDAKAN/GPI1AN RTxDAKBN/GPI1BN TxDAKAN/GPI2AN TxDAKBN/GPI2BN DTCN DONEN PCRA/B RSRA/B TRSRA/B ICTSRA/B DMA INTERFACE GSR CMR1A/B CMR2A/B OMRA/B TRCR A/B FTLR A/B TRMR A/B CID TRxCA/B RTxCA/B RTSBN/SYNOUTBN RTSAN/SYNOUTAN CTSA/BN DCDBN/SYNIBN DCDAN/SYNIAN SPECIAL FUNCTION PINS INTERNAL BUS TRANSMIT A/B TRANS CLK MUX TPRA/B TTRA/B TX SHIFT REG TRANSMIT 16 DEEP FIFO TELRA/B CONTROL CRC GEN SPEC CHAR GEN LOGIC TxD A/B DPLL A/B BRG COUNTER/ TIMER A/B C/T CLK MUX A/B CTCRA/B CTPRHA/B CTPRLA/B CTHA/B CTLA/B
D0-D7
BUS BUFFER
A7 CONTROL LOGIC DTACKN RWN A1-A6 CSN RESETN
RECEIVER A/B INTERRRUPT CONTROL ICRA/B IRQN IERA/B IACKN IVR IVRM IER1 IER2 IER3 DUSCC LOGIC RCVR SHIFT REG RECEIVER 16 DEEP FIFO RFLRA/B CRC ACCUM X1/CLK X2/IDCN OSCILLATOR BISYNC COMPARE LOGIC RCVR CLK MUX RPRA/B RTRA/B S1RA/B S2RA/B RxD A/B
SD00253
1998 Sep 04
5
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
PIN DESCRIPTION
MNEMONIC A1-A6 D0-D7 PIN NO. DIP 4-2, 47-45 31-28, 21-18 PLCC 4-2, 51-49 33-30, 23-20 TYPE I I/O NAME AND FUNCTION Address Lines: Active-high. Address inputs which specify which of the internal registers is accessed for read/write operation. Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All data, command and status transfers between the CPU and the CDUSCC take place over this bus. The data bus is enabled when CSN and R/WN or during interrupt acknowledge cycles and single address DMA acknowledge cycles. Read/Write: A high input indicates a read cycle and a low indicates a write cycle when CEN is active. Chip Select: Active-low input. When active, data transfers between the CPU and the CDUSCC are enabled on D0-D7 as controlled by R/WN and A1-A6 inputs. When CSN is high, the data lines are placed in the 3-State condition (except during interrupt acknowledge cycles and single address DMA transfers). Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of any enabled interrupting condition. The CPU can read the general status register to determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the CDUSCC to output an interrupt vector on the data bus. Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds by either forcing the bus into high-impedance, placing a vector number, call instruction or zero on the data bus. The vector number can be modified or unmodified by the status. If no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance. Crystal or External Clock: When using the crystal oscillator, the crystal is connected between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input. This clock is used to drive the internal bit rate generator, as an optional input to the counter/timer or DPLL, and to provide other required clocking signals. When a crystal is used, a capacitor must be connected from this pin to ground. Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal is connected between pins X1 and X2. This pin can be programmed to provide an interrupt daisy chain active-low output which propagates the IACKN signal to lower priority devices, if no active interrupt is pending. This pin should be left floating when an external clock is used on X1 and X2 is not used as an interrupt daisy chain output. When a crystal is used, a capacitor must be connected from this pin to ground. Master Reset: Active-low. A low on this pin resets the transmitters and receivers and resets the registers shown in Table 1 of the CDUSCC Users' Guide. Reset is asynchronous, i.e., no clock is required. Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external receiver clock is specified for the channel, the input is sampled on the rising edge of the clock. Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted first. This output is in the marking (high) condition when the transmitter is disabled or when the channel is operating in local loopback mode. If external transmitter clock is specified for the channel, the data is shifted on the falling edge of the clock. Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock (1X). Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X), the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system clock (X1 / 2). Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal can be programmed to act as an enable for the transmitter when not in loop mode. The CDUSCC detects logic level transitions on this input and can be programmed to generate an interrupt when a transition occurs. When operating in the BOP loop mode, this pin becomes a loop control output which is asserted and negated by CDUSCC commands. This output provides the means of controlling external loop interface hardware to go on-line and off-line without disturbing operation of the loop.
R/WN CSN
26 25
28 27
I I
IRQN
6
6
O
IACKN
1
1
I
X1/CLK
43
47
I
X2/IDCN
42
46
O
RESETN
7
8
I
RxDA, RxDB
37, 12
40, 14
I
TxDA, TxDB
36, 13
39, 15
O
RTxCA, RTxCB
39, 10
43, 11
I/O
TRxCA, TRxCB
40, 9
44, 10
I/O
CTSA/BN, LCA/BN
32, 17
35, 19
I/O
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6
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
PIN DESCRIPTION (Continued)
MNEMONIC DCDA/BN, SYNIA/BN PIN NO. DIP 38, 11 PLCC 42, 12 TYPE I NAME AND FUNCTION Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is programmable. As a DCD active-low input, it acts as an enable for the receiver or can be used as a general purpose input. For the DCD function, the CDUSCC detects logic level transitions on this pin and can be programmed to generate an interrupt when a transition occurs. As an active-low external sync input, it is used in COP mode to obtain character synchronization for the receiver without receipt of a SYN character. This mode can be used in disc or tape controller applications or for the optional byte timing lead in X.21. Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA controller that one or more characters are available in the receiver FIFO (when the receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation, this output indicates to the DMA controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that can be asserted and negated under program control. Channel A (B) Transmitter DMA Service Request, General Purpose Output, or Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the DMA controller that the transmit FIFO is not full and can accept more data. When not in full-duplex DMA mode, this pin can be programmed as a general purpose or a Request-to-Send output, which can be asserted and negated under program control. Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input: Active-low. For half-duplex single address operation, this input indicates to the CDUSCC that the DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter is enabled) is beginning. For full-duplex single address DMA operation, this input indicates to the CDUSCC that the DMA controller has acquired the bus and that the requested read receiver FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in single address DMA mode. Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low. When the channel is programmed for full-duplex single address DMA operation, this input is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and that the requested load transmitter FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in full-duplex single address DMA mode. Done: Active-low, open-drain. DONEN can be used and is active in both DMA and non-DMA modes. As an input, DONEN indicates the last DMA transfer cycle to the TxFIFO. As an output, DONEN indicates either the last DMA transfer from the RxFIFO or that the transmitted character count has reached terminal count. Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync output, it is asserted one bit time after the specified sync character (COP or BISYNC modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send modem control signal, it functions as described previously for the TxDRQN/RTSN pin. Data Transfer Acknowledge: Active-low, 3-state. DTACKN is asserted on a write cycle to indicate that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to indicate valid data is on the bus. In a write bus cycle, input data is latched by the assertion (falling edge) of DTACKN or by the negation (rising edge) of CSN, whichever occurs first. The signal is negated when completion of the cycle is indicated by negation of CSN or IACKN input, and returns to the inactive state (3-state) a short period after it is negated. In single address DMA mode, input data is latched by the assertion (falling edge) of DTCN or by the negation (rising edge) of the DMA acknowledge input, whichever occurs first. DTACK is negated when completion of the cycle is indicated by the assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first), and returns to the inactive state (3-state) a short period after it is negated. When inactive, DTACKN requires an external pull-up resistor. Device Transfer Complete: Active-low. DTCN is asserted by the DMA controller to indicate that the requested data transfer is complete. +5V Power Input Signal and Power Ground Input
RTxDRQA/BN, GPO1A/BN
34, 15
37, 17
O
TxDRQA/BN, GPO2A/BN, RTSA/BN
33, 16
36, 18
O
RTxDAKA/BN, GPI1A/BN
44, 5
48, 5
I
TxDAKA/BN, GPI2A/BN
35, 14
38, 16
I
DONEN
27
29
I/O
RTSA/BN, SYNOUTA/BN
41, 8
45, 9
O
DTACKN
22
24
O
DTC VCC GND
23 48 24
25 34, 52 26, 13, 41, 7
I I I
1998 Sep 04
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Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
DC ELECTRICAL CHARACTERISTICS4, 5 TA = 0 to +70C, -40 to +85_C, VCC = 5.0V " 10%
SYMBOL VIL VIH PARAMETER Input low voltage: All except X1/CLK X1/CLK Input high voltage: All except X1/CLK X1/CLK Output low voltage:14 All except IRQN IRQN7 Output high voltage:14 (Except open drain outputs) X1/CLK input low current10 X1/CLK input high current10 X2 short circuit current (X2 mode) Input low current RESETN, DTCN, TxDAKA/BN, RTxDAKA/BN Input leakage current Output off current high, 3-State data bus Output off current low, 3-State data bus Open drain output low current in off state: DONEN, DTACKN (3-state) IRQN Open drain output high current in off state: DONEN, IRQN, DTACKN (3-state) Power supply current16 (See Figure 17 for graphs) Input capacitance9 Output capacitance9 Input/output capacitance9 TEST CONDITIONS Min LIMITS Typ Max 0.8 0.8 0 to 70_C -40 to 85_C 2.0 2.3 0.8xVCC VCC 0.5 0.5 VCC-0.5 -150 0.0 150 -15 +15 -0.5 +1 +10 +1 +10 -1 -10 -15 -1 VIN = VCC -1 0 to 70_C -40 to 85_C VCC = GND = 0 VCC = GND = 0 VCC = GND = 0 25 +1 80 95 10 15 20 -0.5 UNIT V V V V V V V V A A mA mA A A A A A A A A A mA pF pF pF
VOL
VOH IILX1 IIHX1 ISCX2 IIL
IOL = 5.3mA (Comm), 4.8mA (Indus) IOL = 8.8mA (Comm), 7.8mA (Indus) IOH = -400A VIN = 0, X2 = GND VIN = VCC, X2 = GND X1 open VIN = 0 VIN = VCC VIN = 0 VIN = 0 to VCC, 0 to 70_C -40 to 85_C VIN = VCC, 0 to 70_C -40 to 85_C VIN = 0 , 0 to 70_C -40 to 85_C VIN = 0
-15 -1 -10
IL IOZH IOZL IODL IODH6 ICC CIN COUT CI/O
NOTES: 1. Stresses above those listed under Abs. Max Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. 2. Clock may be stopped (DC) for testing purposes or when the CDUSCC is in non-operational modes. Operation down to 0 rate clocks is implied by a full static CMOS design, but is not verified in testing or characterization. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature and voltage range. 5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V. All time measurements are referenced at input voltages of 0.2V and 3.0V and output voltages of 0.8V and 2.0V, as appropriate. 6. See Figure 18 for test conditions for outputs. 7. Tests for open drain outputs are intended to guarantee switching of the output transistor. To include noise margin this response is measured from the switching signal midpoint to 0.2 V above the required output level. 8. Execution of the valid command (after it is latched) requires a minimum of three rising edges of X1 (see Figure 19). 9. These values were no explicitly tested; they are guaranteed by design and characterization data. 10. X1/CLK and X2 are not tested with a crystal installed. 11. X1/CLK frequency must be at least as fast as the faster of the receiver or transmitter data rate. 12. The X1 clock drives DTACKN, Baud Rate Generator, command register and the update of the FIFO fill level encoders. The Command Register requires three X1 clocks between two commands; FIFO fill level encoding requires 2.5 to 3.5 X1 cycles. 13. The 68562 bus interface may be operated in two modes; a 68000 compatible mode with automatic DTACK generation and a short chip select mode. DTACKN should not be used externally in the short chip select mode. The DTACKN signal is generated by the assertion of the chip select, and data is latched by assertion of DTACKN or by de-assertion of the chip select, whichever comes first. In single address DMA, the DTACK signal will be de-asserted by the assertion of the DTCN or from the de-assertion of the TxDAKN, whichever occurs first. 14. Also includes X2/IDCN pin in IDC mode. 15. In case of 3-state output, output levels VOL + 0.2 are considered float or high impedance. 16. VO = 0 to VCC, Rx/Tx at 10MHz and X1 at 10MHz
1998 Sep 04
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Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
RESETN
tRELREH
SD00205
Figure 1. Reset Timing LIMITS SYMBOL tRELREH PARAMETER RESETN low to RESETN high
tADVCSL A1-A6
INDUSTRIAL SC68C562 Min 200 Max
COMMERCIAL SC68C562 Min 200 Max
UNIT ns
tRWHCSL R/WN tCSLADI tCSLCSH
tCSHRWL
CSN
tCSHCSL
tCSLDDV D0-D7 INVALID tCSLDDA DTACKN12 tCSLDAL tDALCSH DATA VALID tDDVDAL
tCSHDDF INVALID tCSHDDI
tCSHDAH tCSHDAZ
SD00254
Figure 2. Read Cycle Bus Timing Times represent an X1 clock frequency of 14.745MHz LIMITS SYMBOL tADVCSL tRWHCSL tCSHRWL tCSHCSL tCSLDDV tCSHDDF tDDVDAL tDALCSH tCSLDAL13 tCSHDAH tCSHDAZ tCSLADI tCSLCSH tCSLDDA tCSHDDI PARAMETER A0-A6 valid to CSN low RWN high to CSN low CSN high to RWN low CSN high to CSN low8 CSN low to read data valid CSN high to data bus float Read data valid to DTACKN low9 DTACKN low to CSN high9 CSN low to DTACKN low9 CSN high to DTACKN high CSN high to DTACKN high impedance CSN low to address invalid CSN low to CSN high CSN low to data bus driver active9 CSN high to data invalid 60 150 5 5 20 0 30 ) 1 f CL 140 ) 1.5 f CL 60 90 50 130 10 5 INDUSTRIAL SC68C562 Min 10 10 20 50 150 50 20 0 40 ) 1 f CL 130 ) 1.5 f CL 60 90 Max COMMERCIAL SC68C562 Min 5 5 10 30 130 40 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1998 Sep 04
9
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
tADVCSL A1-A6 tCSHRWH
R/WN tRWLCSL CSN
tCSLADI tCSLCSH
tCSHCSL tDALCSH tCSHWDI
D0-D7 tCSLWDV DTACKN12 tCSHDAH tCSLDAL tCSHDAZ tDALWDI
SD00255
Figure 3. Write Cycle Bus Timing LIMITS SYMBOL tADVCSL tCSLADI tRWLCSL tCSHRWH tCSHCSL tDALCSH tDALWDI tCSLDAL13 tCSHDAH tCSHDAZ tCSLCSH tCSLWDV tCSHWDI PARAMETER A0-A6 valid to CSN low CSN low to A0-A6 invalid RWN low to CSN low CSN high to RWN high CSN high to CSN low8 DTACKN low to CSN high9 DTACKN low to write data invalid9 CSN low to DTACKN low9 CSN high to DTACKN high CSN high to DTACKN high impedance CSN low to CSN high CSN low to write data valid CSN high to write data invalid 150 30 10 INDUSTRIAL SC68C562 Min 10 60 0 0 50 0 0 30 ) 1 f CL 140 ) 1.5 f CL 60 90 130 35 5 Max COMMERCIAL SC68C562 Min 5 50 0 0 30 0 0 40 ) 1 f CL 130 ) 1.5 f CL 60 90 Max ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1998 Sep 04
10
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
IRQN tIALIAH IACKN tIALDDV D0-D7 tIALDDA DTACHN12 tIALDAL tDALIAH tIAHDAZ INVALID tIAHDDI DATA VALID tDDVDAL INVALID tIAHDAH tIAHDDF
SD00256
Figure 4. Interrupt Cycle Timing LIMITS SYMBOL tIALIAH tIALDDA tIALDDV tIAHDDF tDDVDAL tIAHDAH tIAHDAZ tIALDAL tIAHDDI tDALIAH PARAMETER12 IACKN low to IACKN high IACKN low to data bus drivers active9 IACKN low to read data valid IACKN high to data bus floating Read data valid to DTACKN low9 20 80 110 30 ) 1 f CL 5 0 140 ) 1.5 f CL 40 ) 1 f CL 5 0 IACKN high to DTACKN high IACKN high to DTACKN high impedance IACKN low to DTACKN low9 INDUSTRIAL SC68C562 Min 140 5 140 60 20 70 100 130 ) 1.5 f CL Max COMMERCIAL SC68C562 Min 130 10 130 60 Max ns ns ns ns ns ns ns ns ns ns UNIT
IACKN high to data bus invalid DTACKN low to IACKN high9
IACKN tIALDCL IDCN
SD00257
Figure 5. Interrupt Daisy Chain Timing LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min tIALDCL IACKN low to IDCN (daisy chain) low Max 70 COMMERCIAL SC68C562 Min Max 60 ns UNIT
RWN
CSN GPI1_N AND/OR GPI2_N tGIVCSL tCSLGII
SD00258
Figure 6. Input Port Timing 1998 Sep 04 11
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
LIMITS SYMBOL tGIVCSL tCSLGII PARAMETER GPI input valid to CSN low CSN low to GPI input invalid INDUSTRIAL SC68C562 Min 20 40 Max COMMERCIAL SC68C562 Min 20 40 Max ns ns UNIT
RWN
CSN tDALGOV GPO1_N AND/OR GPO2_N DTACKN12 tCSLDAL OLD DATA
tCSHGOV
NEW DATA
SD00259
Figure 7. Output Port Timing LIMITS SYMBOL tDALGOV tCSLDAL
13
PARAMETER DTACKN low to GPO output data valid9 CSN low to DTACKN low9
INDUSTRIAL SC68C562 Min 30 ) 1 f CL Max 40 140 ) 1.5 f CL 100
COMMERCIAL SC68C562 Min 40 ) 1 f CL Max 40 130 ) 1.5 f CL 100
UNIT ns ns ns
tCSHGOV
CSN high to GPO output data valid
1998 Sep 04
12
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
CSN tCSHIRH DTACKN tDALIRH IRQN
SD00260
Figure 8. Interrupt Timing, Write Cycle LIMITS SYMBOL tDALIRH PARAMETER DTACKN low to IRQN high, write cycle9 Write TxFIFO (TxRDY interrupt)9 Write RSR (Rx condition interrupt)9 Write TRSR (Rx/Tx interrupt)9 Write ICTSR (port change and CT interrupt)9 Write TRMSR (Tx Path, Patt recognition)9 tCSHIRH CSN high to IRQN high, write cycle Write TxFIFO (TxRDY interrupt) Write RSR (Rx condition interrupt) Write TRSR (Rx/Tx interrupt) Write ICTSR (port change and CT interrupt) Write TRMSR (Tx Path, Patt recognition)9 100 100 100 100 100 90 90 90 90 90 ns ns ns ns ns 40 40 40 40 40 40 40 40 40 40 ns ns ns ns ns INDUSTRIAL SC68C562 Min Max COMMERCIAL SC68C562 Min Max UNIT
CSN IRQN
tCSHIRH VOL +.5V
SD00261
Figure 9. Interrupt Timing, Read Cycle LIMITS SYMBOL tCSHIRH PARAMETER CSN high to IRQN high, read cycle Read RxFIFO (RxRDY interrupt) 100 90 ns INDUSTRIAL SC68C562 Min Max COMMERCIAL SC68C562 Min Max UNIT
1998 Sep 04
13
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
tCLHCLL tCCHCCL tRCHRCL tTCHTCL X1/CLK CTCLK RxC TxC CLK tCLLCLH tCCLCCH tRCLRCH tTCLTCH
+5V TTL * 470 X1 OPEN X2
*PULL-UP RESISTOR IS NOT REQUIRED WHEN USING CMOS LEVELS
a. Driving X1 from an External Source CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 180 X1 CP1 360k TO 1.5M TO DTACKN BLOCK /2 ALL OTHER BLOCKS X2 CP2 CDUSCC
C1 Y1
C2
SD00262
Figure 10. Receive, Dual Address DMA LIMITS SYMBOL tCLHCLL tCLLCLH tCCHCCL tCCLCCH tRCHRCL tRCLRCH tTCHTCL tTCLTCH fCL fCC fRC fTC fRTC PARAMETER X1/CLK high to low time X1/CLK low to high time CT and DPLL CLK high to low time CT and DPLL CLK low to high time RxC high to low time RxC low to high time TxC high to low time TxC low to high time X1/CLK frequency11, 2 CT CLK frequency RxC frequency (16X or 1X) TxC frequency (16X or 1X) Tx/Rx frequency for FM/Manchester encoding INDUSTRIAL SC68C562 Min 25 25 50 50 55 55 55 55 0 0 0 0 14.7456 16.0 8 8 8 4 Typ Max COMMERCIAL SC68C562 Min 25 25 45 45 50 50 50 50 0 0 0 0 14.7456 16.0 10 10 10 5 Typ Max ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz UNIT
1998 Sep 04
14
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT) tCILTXV
TxC (INPUT) tCILTXV TxD tCILTXV
TxD tCOLTXV TxC (1X OUTPUT) tCOLTXV TxC (1X OUTPUT) tCOLTXV
a. Transmit Timing NRZ
b. Transmit Timing FM0/1, Manchester Encoding
SD00263
Figure 11. LIMITS SYMBOL tCILTXV tCOLTXV* PARAMETER TxC input low (1X) to TxD output TxC input low (16X) to TxD output TxC output low to TxD output (NRZ, NRZI)9 (FM, Manchester)9 INDUSTRIAL SC68C562 Min Max 120 125 25 35 COMMERCIAL SC68C562 Min Max 120 120 20 30 ns ns ns ns UNIT
NOTE: Characterized with no loads on TxD and TxC outputs.* Tester load approximately 50pF.
tRCHSOL RXC (INPUT) tSILRCH SYNIN tRCHSIH tRCHRXI tRXVRCH tRXVRCH
SYNOUTN
RXC (1X) INPUT tRXVRCH RxD tRCHRXI
RxD tRCHRXI
a. Receive Timing NRZ
b. Receive Timing FM0/1, Manchester Encoding
SD00264
Figure 12. LIMITS SYMBOL tRXVRCH PARAMETER RxD data valid to RxC high: For NRZ data For NRZI, Manchester, FM0, FM1 data tRCHRXI RxC high to RxD data invalid: For NRZ data For NRZI, Manchester, FM0, FM1 data tSILRCH tRCHSIH tRCHSOL SYNIN low to RxC high RxC high to SYNIN high RxC high to SYNOUT low 25 30 50 20 110 20 30 50 20 100 ns ns ns ns ns 25 30 20 30 ns ns INDUSTRIAL SC68C562 Min Max COMMERCIAL SC68C562 Min Max UNIT
1998 Sep 04
15
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
tCSLDAL CSN tROLDAL tCSLROL tCSHROH DONEN (OUTPUT) (EOM) tCSLRRH RTxDRQ_N tRRHDAL
DTACKN12
SD00265
Figure 13. Receive, Dual Address DMA LIMITS SYMBOL tCSLROL tCSLRRH tCSHROH tROLDAL tRRHDAL tCSLDAL13 PARAMETER CSN low to Rx DONEN output low CSN low to Rx DMA REQN high CSN high to Rx DONEN output high Rx DONEN output low to DTACKN low9 Rx DMA REQN high to DTACKN low9 CSN low to DTACKN low9 40 40 30 ) 1 f CL 140 ) 1.5 f CL INDUSTRIAL SC68C562 Min Max 110 110 70 40 40 40 ) 1 f CL 130 ) 1.5 f CL COMMERCIAL SC68C562 Min Max 100 100 60 ns ns ns ns ns ns UNIT
1998 Sep 04
16
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
tTOLDAL DONEN (OUTPUT) tCSLTOL CSN tCSLDAL DTACKN12 tCSLDIL
tDALTOH
tCSHTOH
tCSHDIH
tDALDIH DONEN (INPUT) tCSLTRH TxDRQ_N OR RTxDRQ_N tTRHDAL
SD00266
Figure 14. Transmit, Dual Address DMA LIMITS SYMBOL tCSLTOL tCSLTRH tDALDIH tDALTOH tTOLDAL tTRHDAL tCSLDAL13 tCSLDIL tCSHTOH tCSHDIH PARAMETER CSN low to Tx DONEN output low CSN low to Tx DMA REQN high DTACKN low to Tx DONEN input high9 DTACKN low to Tx DONEN output high9 40 40 30 ) 1 f CL 35 70 30 25 140 ) 1.5 f CL Tx DONEN output low to DTACKN low9 Tx DMA REQN high to DTACKN low9 CSN low to DTACKN low9 CSN low to Tx DONEN input low CSN high to Tx DONEN output high CSN high to Tx DONEN input high 0 20 40 40 40 ) 1 f CL 40 60 130 ) 1.5 f CL INDUSTRIAL SC68C562 Min Max 110 110 0 20 Min LIMITS COMMERCIAL SC68C562 Max 100 100 ns ns ns ns ns ns ns ns ns ns UNIT
1998 Sep 04
17
1998 Sep 04
t RALRAH t RAHDDF t RAHRAL t RAHROH t RAHDDI t RALDDV t DTLDDF DATA VALID t DTLDDI t DTLDAZ t RRHDAL INVALID INVALID t RALDDA t RALDAL t DDVDAL t DTLDAH t ROLDAL t RALDTL t DTLDTH t DTLROH t DALDTL t RAHDAZ t RAHDAH t RALROL t RALRRH
Philips Semiconductors
RxDAK_N
D0-D7
DTACKN12
CMOS Dual universal serial communications controller (CDUSCC)
Figure 15. DMA Rx Read Timing--Single Address DMA
18
DTCN
DONEN (OUTPUT)
SD00267
RTxDRQ_N
SC68C562
Product specification
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
DMA Rx Read Timing -- Single Address DMA
LIMITS SYMBOL tRALDDV tDTLDTH tDALDTL tDTLDDF tRALDAL tDDVDAL tDTLDAH tDTLDAZ tRRHDAL tROLDAL tRALRRH tRAHRAL tRALROL tDTLROH tRALRAH tRAHDDF tRALDDA tRAHDDI tDTLDDI tRALDTL tRAHDAH tRAHDAZ tRAHROH PARAMETER Receive DMA ACKN low to read data valid DTCN low to DTCN high DTACKN low to DTCN low9 DTCN low to data bus float Rx DMA ACK low to DTACKN low9 Read data valid to DTACKN low9 DTCN low to DTACKN high DTCN low to DTACKN high impedance Rx DMA REQN high to DTACKN low9 Rx DONEN output low to DTACKN low9 Rx DMA ACKN low to receive DMA REQN high Receive DMA ACKN high to low time Rx DMA ACK low to Rx DONEN output low DTCN low to Rx DONEN output high Rx DMA ACKN low to Rx DMA ACKN high Rx DMA ACKN high to data bus float Rx DMA ACKN low to data bus drivers active9 Rx DMA ACKN high to data bus invalid DTCN low to data bus invalid Rx DMA ACKN low to DTCN low Rx DMA ACKN high to DTACKN high Rx DMA ACKN high to DTACKN high impedance Rx DMA ACKN high to DONEN output high 5 5 5 140 80 110 70 140 60 10 5 5 130 70 100 60 50 100 80 130 60 40 40 100 30 100 70 30 ) 1 f CL 20 80 110 40 40 100 50 0 70 140 ) 1.5 f CL 40 ) 1 f CL 20 80 110 INDUSTRIAL SC68C562 Min Max 140 40 0 60 130 ) 1.5 f CL COMMERCIAL SC68C562 Min Max 130 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1998 Sep 04
19
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
DMA Tx Write Timing -- Single Address DMA
LIMITS SYMBOL tDTLDTH tDALDTL tTALDAL tDTLDAH tDTLDAZ tTRHDAL tTOLDAL tDTLTOH tWDVDTL tDTLWDI tTALTRH tTAHTAL tTALTOL tDILDTL tDTLDIH tTALTAH tTAHWDI tWDVTAH tTAHDAH tTAHDAZ tTAHTOH tDILTAH tTAHDIH tTALDTL PARAMETER DTCN low to DTCN high DTACKN low to DTCN low9 low9 INDUSTRIAL SC68C562 Min 50 0 30 ) 1 f CL 140 ) 1.5 f CL 80 110 40 40 80 40 30 110 40 100 40 40 110 15 60 80 110 70 40 30 110 30 25 100 30 30 100 10 40 70 100 60 30 90 40 20 100 40 40 70 Max COMMERCIAL SC68C562 Min 40 0 40 ) 1 f CL 130 ) 1.5 f CL 80 110 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
Tx DMA ACK low to DTACKN DTCN low to DTACKN high
DTCN low to DTACKN high impedance Tx DMA REQN high to DTACKN low9 Tx DONEN output low to DTACKN Write data valid to DTCN low DTCN low to write data invalid Tx DMA ACKN low to transmit DMA REQN high Transmit DMA ACKN high to low time Tx DMA ACKN low to Tx DONEN output low Transmit DONEN input low to DTCN low DTCN low to transmit DONEN input high Tx ACKN low to Tx ACKN high Tx ACKN high to write data invalid Write data valid to Tx DAKN high Tx DAKN high to DTACKN high Tx DAKN high to DTACKN high impedance Tx DAKN high to DONEN output high DONEN input low to Tx DAKN high Tx DAKN high to DONEN input high Tx DAKN low to DTCN low low9 DTCN low to Tx DONEN output high
1998 Sep 04
20
1998 Sep 04
t TAHDAZ t TAHDAH t TALTAH t DILTAH t TAHWDI t TAHTAL t TAHDIH t WDVDTL t DTLWDI t TALDAL t TALDTL t DTLDAH t DTLDAZ t TRHDAL t TOLDAL t DALDTL t DTLDTH t DILDTL t DTLDIH t DTLTOH t TALTRH t TALTOL t TAHTOH
Philips Semiconductors
t WDVTAH
TxDAKN
D0-D7
12 DTACKN
DTCN
CMOS Dual universal serial communications controller (CDUSCC)
Figure 16. DMA Tx Write Timing--SIngle Address DMA
21
DONEN (input)
TxDRQN
DONEN (output)
SD00269
SC68C562
Product specification
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
50 0C 40 25C 30 ICC 20 70C ICC
50
40
30
20
10
10
0 4 4.5 5 VCC 5.5 6
0 4 6 8 10 Tx/Rx Clk and X1 Frequency
Test Condition: Tx/Rx and X1 Frequency @ 10MHz
Test Condition: VCC = 5V @ 25C
SD00250
Figure 17.
2.7k IRQN 50pF RTxC 50pF 820 DTACKN 150pF +5.0V VCC TRxC
1k DONEN 50pF VCC
710 ALL OTHER OUTPUTS +5.0V 150pF 6.0k
NOTE: All CL includes 50pF stray capacitance, i.e., CL = 150pF = (100pF discrete + 50pF stray).
SD00270
Figure 18. Test Conditions for Outputs
X1/CLK
WRN
COMMAND VALID
SD00219
Figure 19. Command Timing
1998 Sep 04
22
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
RxC
1
2
3
4
5
6
7
8
RxD
LCN a. Loop Control Output Assertion
RxC
1
2
3
4
5
6
7
8
9
RxD
LCN b. Loop Control Output Negation
SD00220
Figure 20. Relationship Between Received Data and the Loop Control Output
1998 Sep 04
23
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
DIP48: plastic dual in-line package; 48 leads (600 mil)
SOT240-1
1998 Sep 04
24
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
PLCC52: plastic leaded chip carrier; 52 leads; pedestal
SOT238-3
1998 Sep 04
25
Philips Semiconductors
Product specification
CMOS Dual universal serial communications controller (CDUSCC)
SC68C562
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 08-98 Document order number: 9397 750 04356
Philips Semiconductors
1998 Sep 04 26

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